CIRCUIT FOR CLOCK SIGNAL RESTORATION, CONTROL LOOP AND SIGNAL SISTEM CONSISTING THEREOF

PROBLEM TO BE SOLVED: To recover a clock signal by using a digital input signal by generating at least two values of phase depending on a level of an output of an oscillator on the occurrence of a state change in a series of input values. SOLUTION: A phase detector 10 in the circuit recovering a clock signal receives the input value obtained from sample value of digital input signal. A sampling frequency for the sampled signal is definitely higher than a nominal frequency of the generated clock signal. The phase detector 10 compares the intensity of oscillator value of a digital oscillator 14 when a series of input signals represent a state change with at least one reference value. When the output value of the oscillator exceeds the reference value, for example, the phase detector 10 provides an output of a positive phase, when the output value of the oscillator is equal to the reference value, the phase detector 10 provides an output of a zero phase, and in the other cases, the phase detector 10 provides an output of a negative phase. A control circuit 16 provides a control instruction for the digital oscillator 14 based on the phase, and generates a count interval depending on the phase.