MEMORY ACCESS CONTROLLER

PROBLEM TO BE SOLVED: To provide a memory access control circuit improved in memory access performance of a main storage using a DRAM, simple and small in circuit configuration and suitable for making it into integrated circuit. SOLUTION: When a memory is divided into plural banks 101-102, chip selection signals (CS0-CSn) are prepared in respective banks. As for a RAS signal 106 and a CAS signal 107, only each one piece thereof is prepared respectively, and the RAS signal 106 and the CAS signal 107 are supplied to all banks. Then, flip-flops 103, 104 of two bits latching the RAS and CAS signals 106, 107 when the chip selection signal is active are awaited in respective banks, and the RAS and CAS signals 106, 107 stored in the flip-flops of respective banks are supplied to DRAM groups 122, 123 in the banks.