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PROBLEM TO BE SOLVED: To eliminate the need of extra memory area for avoiding the parity error by providing an image developing section with means for preventing generation of parity error at the time of reading out a data from a page memory even when the writing operation is performed over an area...

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Bibliographische Detailangaben
1. Verfasser: MASUBUCHI MASANORI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To eliminate the need of extra memory area for avoiding the parity error by providing an image developing section with means for preventing generation of parity error at the time of reading out a data from a page memory even when the writing operation is performed over an area exceeding the physical area of page memory. SOLUTION: At the time of reading out a data from the writing area of an image developing section 1, a parity check suppression signal generation circuit 7 monitors the memory address from the image developing section 1. If the address indicative of a location exceeding a known capacity of page memory 2, a parity check suppression signal is delivered to a parity check mechanism 6 in order to suppress parity check thereat. The parity check suppression signal generation circuit 7 and the parity check mechanism 6 for temporarily suppressing the parity check by receiving a signal therefrom constitute a parity check disable means.