SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device and its manufacturing method, in which a bipolar transistor is mounted together with a MOS transistor with excellent performance of these elements. SOLUTION: N -type regions 2-1 and 2-2 are formed under a buried collector reg...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: NISHIGORI MASATO, ISHIMARU KAZUNARI
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device and its manufacturing method, in which a bipolar transistor is mounted together with a MOS transistor with excellent performance of these elements. SOLUTION: N -type regions 2-1 and 2-2 are formed under a buried collector region of a bipolar transistor and an n-type well region of an MOS transistor on a p-type silicon substrate 1. P-type regions 3-1 and 3-2 are formed under a separation region of the bipolar transistor and a p-type well region of the MOS transistor. An epitaxial layer 5 is formed over these regions 2-1, 2-2, 3-1, and 3-2 on the substrate 1. The epitaxial layer 5 forms each element region layer E1 or E2 included in the bipolar transistor region or the MOS transistor region. In this case, the thickness of the element region layer E2 in the MOS transistor is thicker than that of the element region layer E1 of the bipolar transistor.