PHASE LOCKED LOOP CIRCUIT

PROBLEM TO BE SOLVED: To shorten the pulling-in time from the asynchronous state to the synchronous state at the time or synchronizing the phase and to provide a characteristics having a high tolerance to step out in the synchronous state. SOLUTION: An input clock f1 is inputted to phase comparators 10 and 20 different by pulling-in characteristics. Signals 11 and 21 indicating respective synchronous states of phase comparators 10 and 20 are inputted to a pulling-in detector 40, and the output of this detector 40 selects one of phase comparators 10 and 20 by a switch 30. If both phase comparators 10 and 20 are asynchronous or only the phase comparator 20 us asynchronous, the phase comparator 10 is selected. If they are synchronous, the pulling-in detector 40 selects the phase comparator 20.