IMAGE MEMORY READING CIRCUIT

PROBLEM TO BE SOLVED: To read data from the start address to end address of arbitrary internal cell address. SOLUTION: An enable signal is generated from a read start signal and a borrow signal by an enable generating circuit 14. A shaft register 41 shifts the enable signal by from 2 clocks to 2 +2...

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Bibliographische Detailangaben
Hauptverfasser: KOBAYASHI KIYOSHI, TAMURA YASUHIRO, SHIMOYAMA MASAFUMI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To read data from the start address to end address of arbitrary internal cell address. SOLUTION: An enable signal is generated from a read start signal and a borrow signal by an enable generating circuit 14. A shaft register 41 shifts the enable signal by from 2 clocks to 2 +2 clocks. A counter enable signal is generated by an AND gate 16. A start shift selector 42 selects the signal shifted by the shift register 41 just for the value of the start address inside a 2 + start address. An end shift selector 43 selects the signal shifted by the shift register 41 just for the value of the internal end address of the 2 + end address + '1'. A comparator 44 compares the value of the internal start address with the value of the internal end address, and an AND/OR selector 47 selects the AND or OR of the output of the start shift selector 42 and the output of the end shift selector 43.