PREFETCH-TYPE COLUMN DECODER AND SEMICONDUCTOR MEMORY DEVICEWITH IT

PROBLEM TO BE SOLVED: To attain a more stable design margin in a chip by controlling a column select gate on a corresponding column select line on a prefetch system memory cell thereby making a semiconductor memory operable at a frequency lower than an external operation frequency. SOLUTION: Memory cells CELL 50 to be prefetched simultaneously are connected with the column select gates 3, 5,... 11 of an NMOS transistor for selecting the data of memory cell 50 on the column select lines CSL0-CSL511. Data on the pair of I/O lines connected with the column select gate is amplified by sense amplifiers 100, 200 and outputted on a data input line DIO. This arrangement realizes a column decoder operable constantly at a frequency lower than the external operation frequency in prefetch system while provided a more stabilized design margin in the design of a chip.