SEMICONDUCTOR MEMORY DEVICE

PURPOSE: To reduce peak current by an arrangement wherein multiple row decoder groups can be operated while being divided by the output signals from multiple relays being controlled by a block select address signal. CONSTITUTION: When output signals Axi , Axi from a row address buffer 1 are inputted, in High state, to the NAND gate G5 of a row predecoder 2, an output signal passed through inverters G6, G7 goes Low before being inputted to first through N-th repeaters R1-RN. If only the BS1 among block select address signals BS1-BSN is High at that time, only the first relay in a relay group 10 is enabled and a first row decoder group D1 is driven to enable the word line for the first memory block. Assuming the size of the row predecorder 2 is W, it is reduced by a factor of N and the peak current can be reduced because the load at the output end is light.