CLOCK SIGNAL GENERATION CIRCUIT

PURPOSE: To reduce a signal error rate by providing a control means which takes synchronism following a timing signal inputted from the outside in a synchronous following mode and maintains a clock signal phase set by a synchronous following mode in a synchronous maintaining mode. CONSTITUTION: This circuit is provided with the synchronous following mode and the synchronous maintaining mode, and equipped with a control part 12 which takes the synchronism following the timing signal inputted from the outside in the synchronous following mode, and maintains the clock signal phase set in the synchronous following mode in the synchronous maintaining mode. The control part 12 maintains the clock signal phase of the synchronous maintaining mode according to the output of a reference frequency oscillator 4. The control part 12 detects a timing signal level when the synchronous following mode is set, and connects the synchronous following mode as it is when the timing signal level is larger than a threshold value. When the timing signal level is detected and it is smaller than the threshold value. the synchronous maintaining mode is set.