VERTICAL TRANSISTOR AND ITS MANUFACTURE

PROBLEM TO BE SOLVED: To improve process margin by reducing a leakage current and forming a self-aligned type contact hole by a method, wherein a source region consisting of the third part of a third conductive pattern which comes in contact with a channel region, is formed inside a second contact hole formed by the pattern of a third insulating layer. SOLUTION: A second part, i.e., a channel region of a third conductive layer pattern 114 which comes in contact with a drain region, is formed in a hole formed by gate-insulating layers 113. Then the third part, i.e., a source region, of the third conductive layer 114, having impurity density identical to that of the drain region, is formed in the hole of a third insulating layer pattern 110a, while the layer 114 makes contact with the channel region. At this point, a silicon layer is grow on the channel region and the source region by performing an epitaxial growth method. Then, after a silicon layer has been grown on the whole surface of the semiconductor substrate where the source region is formed, a fourth conductive layer pattern 115 which comes in contact with the source region, is formed by patterning the fourth conductive layer, thereby obtaining a three dimensional transistor.