POLYSILICON GATE OF SEMICONDUCTOR MEMORY DEVICE AND ITS MANUFACTURE

PROBLEM TO BE SOLVED: To suppress the influence on a gate insulation film to avoid the threshold voltage variation or dielectric breakdown of an MOS transistor by suppressing the charge storage in the polysilicon gate in a plasma etching process. SOLUTION: The polysilicon gate is formed by forming a...

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Bibliographische Detailangaben
Hauptverfasser: CHIYOU SEIKI, RI KEIKON, CHIYOU JIYUNCHIN, KOU NEII
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To suppress the influence on a gate insulation film to avoid the threshold voltage variation or dielectric breakdown of an MOS transistor by suppressing the charge storage in the polysilicon gate in a plasma etching process. SOLUTION: The polysilicon gate is formed by forming a polysilicon layer 610 on an active region 500 and contact polysilicon layer 620 outside this region 500 and connecting them through a conductive material 600 in a wiring process, etc. A plasma etching process causes the charge storage having a less influence of the polysilicon layer 610 on the gate insulation film, than in prior art, thereby reducing the stored change quantity and hence the influence on the gate insulation film.