WIRING FORMATION OF SEMICONDUCTOR ELEMENT
PROBLEM TO BE SOLVED: To provide a wire forming method for semiconductor devices having high reliability by preventing the production of protrusions in contact holes. SOLUTION: After forming a first insulating layer 52 patterned on a semiconductor substrate 50 and forming a lower capping layer 54 on...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | PROBLEM TO BE SOLVED: To provide a wire forming method for semiconductor devices having high reliability by preventing the production of protrusions in contact holes. SOLUTION: After forming a first insulating layer 52 patterned on a semiconductor substrate 50 and forming a lower capping layer 54 on it, first contact holes are formed by etching the lower capping layer and the first insulating layer. After forming a wire layer 58 following this, this wire layer and the lower capping layer 54 are CMPed until the first insulating layer 52 is exposed, and a second insulating layer 60 is formed on the whole surface of the substance obtained as the result. After that, this second insulating layer 60 and the first insulating layer 52 are etched, and second contact holes are formed. |
---|