CURRENT MODE CIRCUIT FOR FORMING EACH PRODUCT BIT IN WALLACETREE MULTIPLIER

PROBLEM TO BE SOLVED: To provide a wallace tree multiplier of a VLSI configuration adopting the current mode circuit realized by a chip area whose design is easily confirmed. SOLUTION: The current mode circuit includes pluralities of input terminals PP1-PP15 that receive a binary input signal and pl...

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Hauptverfasser: SHIBARINGU ESU MAHANTO SHIETSUTEI, KAARU II REMONZU JIYUNIA
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a wallace tree multiplier of a VLSI configuration adopting the current mode circuit realized by a chip area whose design is easily confirmed. SOLUTION: The current mode circuit includes pluralities of input terminals PP1-PP15 that receive a binary input signal and pluralities of transistors(TRs) 20 are each coupled to an input terminal and produce a current iO into a summing node 24 when the input terminal coupled thereto has a binary one signal thereon and no current when the input terminal is a binary zero. The current in the summing node 24 is shunted to ground by a diode 30. A high order sum bit C3OUT is produced by a current sensing circuit including TRs 32, 34 when the current into the summing node 24 is equal to or higher than 0. Finally, a 4th-order sum bit SUM is generated.