JPH0821647B

A high density package for a plurality of integrated circuit chips (14) is described, the package including a number of planar subunits. A subunit includes first (50) and second (64) planar metal plates and a spacer metal plate (56) sandwiched therebetween. Each spacer metal plate is provided with a plurality of circuit-receiving apertures (58). A planar circuit carrier is provided for each aperture in the spacer metal plate. One face of each circuit carrier includes a plurality of bonded chips. Each circuit carrier is positioned in a circuit-receiving aperture so that rear aspects of the bonded chips bear upon the second planar metal plate. Each circuit carrier has a connector region (74, 78) which extends out from between the first planar metal plate and the metal spacer plate at one extremity of each circuit-receiving aperture. A circuit card (76) is positioned at that extremity and has a plurality of interconnection areas, one for each extended connector region. The circuit card has its major surface oriented parallel to the metal plates so that the entire package presents an overall planar configuration.