MEMORY DECODER

PURPOSE: To provide a memory decoder capable of performing read/write on all the memories by a small number of memory selection signals when a large number of memories are used. CONSTITUTION: An address decoder 101 decodes memory addresses 111 to 112, and sets a state in which read/write on the memo...

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Hauptverfasser: INUDOU KOUSUKE, ORIHASHI RITSURO
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE: To provide a memory decoder capable of performing read/write on all the memories by a small number of memory selection signals when a large number of memories are used. CONSTITUTION: An address decoder 101 decodes memory addresses 111 to 112, and sets a state in which read/write on the memory connected to an output side can be permitted, and moreover, specifies the memory from which a readout signal 114 and a write signal 115 are supplied by the logic value of a memory address 113. The read/write on target memory can be performed by configuring a circuit so as to unify the memory on which the read/write can be performed and also, from which the readout signal or write signal can be supplied.