PLL CIRCUIT

PURPOSE: To extend the lock range of a PLL circuit to generate a system clock to be used for video digital processing. CONSTITUTION: A voltage controlled oscillation circuit 4 to generate the first clock signal of required frequency, a frequency converting part 5 to convert the frequency of the first clock signal and output it as the second clock signal of the required frequency, a frequency divider 6 to frequency-divide the second clock signal into the required frequency, a phase comparing part 2 to phase- compare the clock signal from the frequency divider and a horizontal synchronizing signal S1, a low pass filter 3 to take an oscillation frequency control signal out of phase comparison output from the phase comparing part and impress the same oscillation frequency control signal to the voltage controlled oscillation circuit, a frequency comparing part 7 to compare the horizontal synchronizing signal and the second clock signal and output the signal based on this comparison, and a control part 8 to control the frequency converting part so that the second clock signal becomes the required frequency on the basis of a compared result by the frequency comparing part are provided.