DIGITAL PHASE LOCKED LOOP CIRCUIT

PURPOSE: To normally reproduce data even when a frequency is shifted by providing a bit discarding circuit in a loop of an integration circuit and discarding lower-order bits to make an output of the integration circuit approach zero. CONSTITUTION: A phase where a sampled input signal is intersected with a reference level is calculated, and the calculated phase information is compared with an output phase of a phase oscillator by a phase comparator 2 to output a phase error signal to a loop filter 203. The output of the comparator 2 is added to an output signal of the comparator 2 before one sample by the integration circuit consisting of an adder 13 and a delay circuit 14 in the filter 203. The lower-order bits are discarded by the bit discarding circuit 15 to make the input data approach zero. Thus, the phase locked loop having reduced malfunction can be constituted in a simple circuit configuration, and a clock extracting circuit of high performance can be obtained.