FAULT PROCESSING METHOD IN MEMORY ACCESS

PURPOSE:To prevent a system from going down due to a fault occurring in memory access by informing a processor making access memory of the occurrence of the fault and an address where the fault occurs when a write address error is detected and advancing processing to the next one after completing th...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: IMASHIRO HIDEKI, KIRYU YOSHIO
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To prevent a system from going down due to a fault occurring in memory access by informing a processor making access memory of the occurrence of the fault and an address where the fault occurs when a write address error is detected and advancing processing to the next one after completing the processing including the present memory access. CONSTITUTION:A computer system is constituted of an instruction processor 1, a memory device 2, and a fault processor 3. For example, when an error occurs in an inputted write address, it is detected by a parity check(PC) circuit 24, and a write operation is suppressed by stopping the operation of a memory control circuit 23 by an error signal 240, and a fault processing request is issued to the fault processor 3. The fault processor 3, after recording the address where the fault occurs. issues a write fault report to the instruction processor 1 via the memory device 2. The intruction processor 1 receiving the fault report completes the processing in which the fault occurs, and advances the processing to the next one, and prohibits the use of the address where the fault occurs in the following processing.