FIFO MEMORY DEVICE AND METHOD FOR IMPROVING RELIABILITY
PURPOSE:To detect the failure of an internal memory by an external circuit or the like without preparing a detecting means by including a diagnostic circuit for diagnosing the failure of the memory in an FIFO memory. CONSTITUTION:A diagnostic part 1a in a diagnostic circuit 20 is connected to a data...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | PURPOSE:To detect the failure of an internal memory by an external circuit or the like without preparing a detecting means by including a diagnostic circuit for diagnosing the failure of the memory in an FIFO memory. CONSTITUTION:A diagnostic part 1a in a diagnostic circuit 20 is connected to a data memory body 6 through a write address bus 2, a write data bus 3, a write control signal 10, a read address bus 4, a read data bus 5 and a read control signal 13, and at the time of detecting abnormality by diagnosis, informs an external control part of a non-coincidence signal 7. Namely the diagnostic part 1a compares written data with read data, and when both the data are different from each other, informs the external control part of the signal 7. The external control part records the signal 7 and stops the operation of an FIFO memory device 21 when necessary. Thus, data are written/read out in/from all addresses in the body 6 and the non-coincidence of data is detected. |
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