ELEVATED GATE FIELD-EFFECT TRANSISTOR STRUCTURE AND ITS PREPARATION

PURPOSE: To restrain decrease in the saturated drain-source current while the yield voltage between the gate and the drain is improved, by making the bottom surface of the gate higher than the upper surface of an active region in the peripheral part of the bottom surface by etching the active region surfaces on both sides of the gate. CONSTITUTION: After a field oxide layer 14 formed on a substrate 12 is patterned, an active layer 16 is formed by ion implantation. A gate 20 is formed on the upper surface 44 of the active layer 16, and patterning is performed. Etching is performed by using the gate 20 and the field oxide layer 14 as masks, and the uppermost drain surface 34 and the uppermost source surface 36 of the active layer 16 are made lower than the original upper surface 44. After spacers 22, 24 are formed adjacently to the gate 20, a photoresist layer 50 is deposited, an end portion 52 is defined by patterning, and a source region 26 and a drain region 28 are formed by implanting Si ions. After the photoresist layer 50 is eliminated, a source region 30 and a drain electrode 32 are formed.