MISMATCHED TRANSPOSITION SUPPRESSION METHOD FOR SILICON WAFER AND SILICON WAFER STRUCTURE
PURPOSE: To improve electrical characteristics of a silicon wafer by avoiding mismatched dislocation, which is inevitably caused by implantation of a high concentration of impurities in the silicon wafer and to improve mechanical characteristics by reducing its surface roughness. CONSTITUTION: An an...
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| creator | CHIYURU HI HAN HO JIYUN RII CHIYUUN KI KIMU |
| description | PURPOSE: To improve electrical characteristics of a silicon wafer by avoiding mismatched dislocation, which is inevitably caused by implantation of a high concentration of impurities in the silicon wafer and to improve mechanical characteristics by reducing its surface roughness. CONSTITUTION: An annular impurity implantation interrupting region 15 is formed on a silicon wafer 11 for interrupting mismatched dislocation which propagates through the silicon wafer 11. An inner radius impurity implantation region 17 is encircled by the area 15 and the propagation of dislocation to this region is prevented. In this way, a layer in which a high concentration of impurities without dislocation is implanted is formed. |
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CONSTITUTION: An annular impurity implantation interrupting region 15 is formed on a silicon wafer 11 for interrupting mismatched dislocation which propagates through the silicon wafer 11. An inner radius impurity implantation region 17 is encircled by the area 15 and the propagation of dislocation to this region is prevented. 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In this way, a layer in which a high concentration of impurities without dislocation is implanted is formed.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</subject><subject>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</subject><subject>MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICALDEVICES</subject><subject>MICROSTRUCTURAL TECHNOLOGY</subject><subject>PERFORMING OPERATIONS</subject><subject>PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS</subject><subject>TRANSPORTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1995</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZIj09Qz2dQxx9nB1UQgJcvQLDvAP9gzx9PdTCA4NCAhyDQ4GsX1dQzz8XRTc_IMUgj19PJ2BQuGObq5BCo5-LmgiwSFBoc4hoUGuPAysaYk5xam8UJqbQdHNFWiRbmpBfnxqcUFicmpeakm8V4CHgbmRmbGxmbmjMTFqAIVGMmU</recordid><startdate>19951013</startdate><enddate>19951013</enddate><creator>CHIYURU HI HAN</creator><creator>HO JIYUN RII</creator><creator>CHIYUUN KI KIMU</creator><scope>EVB</scope></search><sort><creationdate>19951013</creationdate><title>MISMATCHED TRANSPOSITION SUPPRESSION METHOD FOR SILICON WAFER AND SILICON WAFER STRUCTURE</title><author>CHIYURU HI HAN ; HO JIYUN RII ; CHIYUUN KI KIMU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH07263367A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1995</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</topic><topic>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</topic><topic>MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICALDEVICES</topic><topic>MICROSTRUCTURAL TECHNOLOGY</topic><topic>PERFORMING OPERATIONS</topic><topic>PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS</topic><topic>TRANSPORTING</topic><toplevel>online_resources</toplevel><creatorcontrib>CHIYURU HI HAN</creatorcontrib><creatorcontrib>HO JIYUN RII</creatorcontrib><creatorcontrib>CHIYUUN KI KIMU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHIYURU HI HAN</au><au>HO JIYUN RII</au><au>CHIYUUN KI KIMU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MISMATCHED TRANSPOSITION SUPPRESSION METHOD FOR SILICON WAFER AND SILICON WAFER STRUCTURE</title><date>1995-10-13</date><risdate>1995</risdate><abstract>PURPOSE: To improve electrical characteristics of a silicon wafer by avoiding mismatched dislocation, which is inevitably caused by implantation of a high concentration of impurities in the silicon wafer and to improve mechanical characteristics by reducing its surface roughness. CONSTITUTION: An annular impurity implantation interrupting region 15 is formed on a silicon wafer 11 for interrupting mismatched dislocation which propagates through the silicon wafer 11. An inner radius impurity implantation region 17 is encircled by the area 15 and the propagation of dislocation to this region is prevented. In this way, a layer in which a high concentration of impurities without dislocation is implanted is formed.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICALDEVICES MICROSTRUCTURAL TECHNOLOGY PERFORMING OPERATIONS PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS SEMICONDUCTOR DEVICES TECHNICAL SUBJECTS COVERED BY FORMER USPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS TRANSPORTING |
| title | MISMATCHED TRANSPOSITION SUPPRESSION METHOD FOR SILICON WAFER AND SILICON WAFER STRUCTURE |
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