DATA OUTPUT BUFFER

PURPOSE: To improve the stability of output speed and valid data generation by controlling a buffer enable signal while using a control transmission gate and a control latch part. CONSTITUTION: Data DO and bar DO are inputted to an input part 90. In response to the clock of a clock signal CLK, the input part 90 is conducted and the data DO and bar DO are latched by latch parts 85 and 97. After a signal bar CAS is inputted, a buffer enable signal TRST is generated. Then, this signal is inputted through a control gate 120 to a control latch part 145 and latched. Therefore, a control node N2 is turned to the potential of logic 'high' synchronously with a fetch clock showing the start of valid data generation. According to such a state, data drivers 95 and 100 are activated and output data DOUT are generated. Thus, the stability of output speed and valid data generation is improved, unwanted data generation is prevented and reliability is improved.