METHOD AND CIRCUIT FOR ERASING FLOATING-GATE TYPE MEMORY CELL ARRAY

PURPOSE: To obtain a simple, economical and easy-to-realize method and circuit for attaining the narrowing and the self-limited erasing of the distribution of the erasing threshold value voltage of the memory cell array of a floating gate type. CONSTITUTION: The control gate 14 of the memory cell 10 of the floating gate type is connected to a control gate voltage Vg, a source 11 is connected with source potential Vs higher than the voltage Vg, and a drain 12 is connected with a drain structure DS. As the result that the sub-circuit DS is provided with a drain voltage Vd between the voltage Vg and the potential Vs and with impedance, which is low enough to allow a current to flow between the source 11 and the drain 12 at some time in the middle of erasing operation, the distribution of an optimum threshold value voltage is made possible. Desirably, the part of a drain voltage Vd is fed back by way of a feedback terminal 27 and the control gate 14 so as to stop erasing operation at an optimum point.