MANUFACTURE OF INTEGRATED CIRCUIT DEVICE WITH MOS TRANSISTOR

PURPOSE: To manufacture a MOS transistor, having a limited channel length by forming a second opening of a depth at least equal to the thickness of the sum of a drain region and a channel region, in a lamination, and providing a gate dielectric material and a gate electrode on the surface therof. CONSTITUTION: In a layer structure comprising a first layer 5, a second layer 6 and a third layer 7, a second opening 8 is formed by etching as far as the surface of a source terminal region 2, using a lithographic process, and a gate dielectric material 9 is formed continuously by oxidization. In that case, an oxidization time is controlled so that the thickness of the gate dielectric material 9 of the surface of the second layer 6 is about 5 nm. Then a space which remains inside of the second opening 8 is filled with polysilicon doped with n , to form a gate electrode 10. Thereby a MOS transistor, having a channel length limited in a range not exceeding 50 nm, is manufactured.