SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

PURPOSE:To improve subthreshold characteristics, and to conduct a low voltage operation and a high-speed operation at low current consumption by a method wherein the first conductive type impurity layer under a channel formation region is formed shallower than that under a source-drain diffusion lay...

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1. Verfasser: MIZUNO TATSUO
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To improve subthreshold characteristics, and to conduct a low voltage operation and a high-speed operation at low current consumption by a method wherein the first conductive type impurity layer under a channel formation region is formed shallower than that under a source-drain diffusion layer in the longitudinal direction of a substrate. CONSTITUTION:An element isolation silicon oxide film 102 is formed on an N-type semiconductor substrate 101. Then, the second silicon oxide film 103 and a P-type well region 104 are formed by a thermal oxidization method. Then, the silicon oxide film formed by oxidization is removed, a gate oxide film 105 of about 10 to 20nm is grown by a thermal oxidization method, and after a polycrystalline silicon layer of about 100 to 500nm has been formed by a CVD method, phosphorus is implanted by a thermal diffusion method, a dry etching method is conducted after patterning, and a gate electrode 106 is formed. Then, arsenic is implanted by an ion-implanting method for formation of the source and the drain regions of a MOS type transistor, and a high concentration N-type diffusion layer 107 is formed.