CONTROL METHOD FOR VIRTUAL MEMORY DEVICE

PURPOSE:To increase the speed of address space generating processing by reducing overhead in the generation of an address translation table when address space is generated. CONSTITUTION:When a program under execution in one address space generates new address space, the entry of the address translat...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: ARAI TOSHIAKI, HOSOUCHI MASAAKI, ABE MASAKATSU, UKAI YOSHIO
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To increase the speed of address space generating processing by reducing overhead in the generation of an address translation table when address space is generated. CONSTITUTION:When a program under execution in one address space generates new address space, the entry of the address translation table of high-order level for a virtual memory area in which a real memory area is allocated to the address space on a generation request side is copied on a corresponding address translation table in the address space to be generated newly, and the address translation table of low-order level is shared with each address space. In other words, it is possible to share the real memory area between generation request side address space 100a and relational address space such as the address space 100b to be generated and to arrange another segments to a read-only area and a write-only area, separately by sharing a page table like a shared page table 120b and a copy-on reference page table 120c(including a copy-on reference state and copy-on write state).