SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
PURPOSE:To reduce the change in a gate voltage of a precharging MOSFET and to reduce current consumption in a precharge circuit by making complementary bit lines of non-selection the precharge as it is. CONSTITUTION:In a unit precharge circuit UPRO, an SPDO circuit supplying a control signal to the...
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creator | UCHIDA MAKIO NUNOKAWA MASAYOSHI HASEGAWA MASAMI SATO YOICHI SHINAGAWA SATOSHI SHIMONO KAN MIYASAKA MASAYUKI IIOKA YOSHIO |
description | PURPOSE:To reduce the change in a gate voltage of a precharging MOSFET and to reduce current consumption in a precharge circuit by making complementary bit lines of non-selection the precharge as it is. CONSTITUTION:In a unit precharge circuit UPRO, an SPDO circuit supplying a control signal to the precharging MOSFETs Q3, Q4 of the complementary bit lines B0, B0B is provided. Then, at the time of the memory access performing the read or the write, the precharging MOSFETs Q3, Q4 provided on a selection bit line are turned off by the SPD circuit, and the precharging MOSFETs on other non-selection bit lines are turned on, and the precharging operation is continued. Thus, the necessity that all bit lines are charged and discharged is eliminated, and power consumption is reduced. |
format | Patent |
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CONSTITUTION:In a unit precharge circuit UPRO, an SPDO circuit supplying a control signal to the precharging MOSFETs Q3, Q4 of the complementary bit lines B0, B0B is provided. Then, at the time of the memory access performing the read or the write, the precharging MOSFETs Q3, Q4 provided on a selection bit line are turned off by the SPD circuit, and the precharging MOSFETs on other non-selection bit lines are turned on, and the precharging operation is continued. Thus, the necessity that all bit lines are charged and discharged is eliminated, and power consumption is reduced.</description><edition>6</edition><language>eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SELECTING ; STATIC STORES</subject><creationdate>1995</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19950512&DB=EPODOC&CC=JP&NR=H07122074A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19950512&DB=EPODOC&CC=JP&NR=H07122074A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>UCHIDA MAKIO</creatorcontrib><creatorcontrib>NUNOKAWA MASAYOSHI</creatorcontrib><creatorcontrib>HASEGAWA MASAMI</creatorcontrib><creatorcontrib>SATO YOICHI</creatorcontrib><creatorcontrib>SHINAGAWA SATOSHI</creatorcontrib><creatorcontrib>SHIMONO KAN</creatorcontrib><creatorcontrib>MIYASAKA MASAYUKI</creatorcontrib><creatorcontrib>IIOKA YOSHIO</creatorcontrib><title>SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE</title><description>PURPOSE:To reduce the change in a gate voltage of a precharging MOSFET and to reduce current consumption in a precharge circuit by making complementary bit lines of non-selection the precharge as it is. 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Thus, the necessity that all bit lines are charged and discharged is eliminated, and power consumption is reduced.</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SELECTING</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1995</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAPdvX1dPb3cwl1DvEPUvD0C3F1D3IMcXVRcPYMcg71DFFwcQ3zdHblYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxXgEeBuaGRkYG5iaOxsSoAQD_ciQn</recordid><startdate>19950512</startdate><enddate>19950512</enddate><creator>UCHIDA MAKIO</creator><creator>NUNOKAWA MASAYOSHI</creator><creator>HASEGAWA MASAMI</creator><creator>SATO YOICHI</creator><creator>SHINAGAWA SATOSHI</creator><creator>SHIMONO KAN</creator><creator>MIYASAKA MASAYUKI</creator><creator>IIOKA YOSHIO</creator><scope>EVB</scope></search><sort><creationdate>19950512</creationdate><title>SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE</title><author>UCHIDA MAKIO ; NUNOKAWA MASAYOSHI ; HASEGAWA MASAMI ; SATO YOICHI ; SHINAGAWA SATOSHI ; SHIMONO KAN ; MIYASAKA MASAYUKI ; IIOKA YOSHIO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH07122074A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1995</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SELECTING</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>UCHIDA MAKIO</creatorcontrib><creatorcontrib>NUNOKAWA MASAYOSHI</creatorcontrib><creatorcontrib>HASEGAWA MASAMI</creatorcontrib><creatorcontrib>SATO YOICHI</creatorcontrib><creatorcontrib>SHINAGAWA SATOSHI</creatorcontrib><creatorcontrib>SHIMONO KAN</creatorcontrib><creatorcontrib>MIYASAKA MASAYUKI</creatorcontrib><creatorcontrib>IIOKA YOSHIO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>UCHIDA MAKIO</au><au>NUNOKAWA MASAYOSHI</au><au>HASEGAWA MASAMI</au><au>SATO YOICHI</au><au>SHINAGAWA SATOSHI</au><au>SHIMONO KAN</au><au>MIYASAKA MASAYUKI</au><au>IIOKA YOSHIO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE</title><date>1995-05-12</date><risdate>1995</risdate><abstract>PURPOSE:To reduce the change in a gate voltage of a precharging MOSFET and to reduce current consumption in a precharge circuit by making complementary bit lines of non-selection the precharge as it is. CONSTITUTION:In a unit precharge circuit UPRO, an SPDO circuit supplying a control signal to the precharging MOSFETs Q3, Q4 of the complementary bit lines B0, B0B is provided. Then, at the time of the memory access performing the read or the write, the precharging MOSFETs Q3, Q4 provided on a selection bit line are turned off by the SPD circuit, and the precharging MOSFETs on other non-selection bit lines are turned on, and the precharging operation is continued. Thus, the necessity that all bit lines are charged and discharged is eliminated, and power consumption is reduced.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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subjects | ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY INFORMATION STORAGE PHYSICS SELECTING STATIC STORES |
title | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
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