SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PURPOSE:To reduce the change in a gate voltage of a precharging MOSFET and to reduce current consumption in a precharge circuit by making complementary bit lines of non-selection the precharge as it is. CONSTITUTION:In a unit precharge circuit UPRO, an SPDO circuit supplying a control signal to the...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: UCHIDA MAKIO, NUNOKAWA MASAYOSHI, HASEGAWA MASAMI, SATO YOICHI, SHINAGAWA SATOSHI, SHIMONO KAN, MIYASAKA MASAYUKI, IIOKA YOSHIO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PURPOSE:To reduce the change in a gate voltage of a precharging MOSFET and to reduce current consumption in a precharge circuit by making complementary bit lines of non-selection the precharge as it is. CONSTITUTION:In a unit precharge circuit UPRO, an SPDO circuit supplying a control signal to the precharging MOSFETs Q3, Q4 of the complementary bit lines B0, B0B is provided. Then, at the time of the memory access performing the read or the write, the precharging MOSFETs Q3, Q4 provided on a selection bit line are turned off by the SPD circuit, and the precharging MOSFETs on other non-selection bit lines are turned on, and the precharging operation is continued. Thus, the necessity that all bit lines are charged and discharged is eliminated, and power consumption is reduced.