PIPELINE FLOATING-POINT PROCESSOR AND EXECUTION OF ITS MULTIPLICATION AND ADDITION INSTRUCTION SEQUENCE

PURPOSE: To unnecessitate the wait cycle of a high-speed multiplying/adding instruction in a pipeline floating point processor. CONSTITUTION: An adding pipeline is reconstituted and normalized data are fed back from a multiplier M through a path ND to aligning devices AL1 and AL2. Next, while consid...

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Hauptverfasser: SON DAOOTSURONGU, YUURUGEN HAASU, RORUFU MIYURAA
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE: To unnecessitate the wait cycle of a high-speed multiplying/adding instruction in a pipeline floating point processor. CONSTITUTION: An adding pipeline is reconstituted and normalized data are fed back from a multiplier M through a path ND to aligning devices AL1 and AL2. Next, while considering possibility of digit of zero at the head of a product, the feed of one digit to left and special zero setting of protection digit by Z1 and Z2 are performed on both the sides of a data path. Then, an exponent is formed from 9 bits for recognizing overflow and underflow, and the result of the exponent is reset to zero for the underflow by skipping by a true zero value unit (T/C).