JPH069116B

A semiconductor integrated circuit device has an address decoder which is constructed of a plurality of MOSFETs implemented in a switch tree. The switch tree includes first and second switch tree portions which are controlled 'on' and 'off' by the same input signals. A first swit...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	OOKUBO CHIKAO, TACHIMORI HIROSHI, FUKUDA HIROSHI, FUKAZAWA TAKESHI, TAKAHASHI OSAMU
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE STATIC STORES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	OOKUBO CHIKAO TACHIMORI HIROSHI FUKUDA HIROSHI FUKAZAWA TAKESHI TAKAHASHI OSAMU
description	A semiconductor integrated circuit device has an address decoder which is constructed of a plurality of MOSFETs implemented in a switch tree. The switch tree includes first and second switch tree portions which are controlled 'on' and 'off' by the same input signals. A first switch branch in the first switch tree portion, which is constructed of a comparatively small number of MOSFETs, and a second switch branch in the second switch tree portion, which is constructed of a comparatively large number of MOSFETs, are controlled 'one' and 'off' by the same input signal, while a second switch branch in the first switch tree portion, which is constructed of a comparatively large number of MOSFETs, and a first switch branch in the second switch tree portion, which is constructed of a comparatively small number of MOSFETs, are controlled 'on' and 'off' by the same input signal. This construction is effective to lessen an increase in the number of MOSFETs which are to be coupled to the input lines of the address decoder.
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH069116BB2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH069116BB2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH069116BB23</originalsourceid><addsrcrecordid>eNrjZODyCvAwMLM0NDRz4mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8QgNTkbGxKgBADGfG6Y</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>JPH069116B</title><source>esp@cenet</source><creator>OOKUBO CHIKAO ; TACHIMORI HIROSHI ; FUKUDA HIROSHI ; FUKAZAWA TAKESHI ; TAKAHASHI OSAMU</creator><creatorcontrib>OOKUBO CHIKAO ; TACHIMORI HIROSHI ; FUKUDA HIROSHI ; FUKAZAWA TAKESHI ; TAKAHASHI OSAMU</creatorcontrib><description>A semiconductor integrated circuit device has an address decoder which is constructed of a plurality of MOSFETs implemented in a switch tree. The switch tree includes first and second switch tree portions which are controlled 'on' and 'off' by the same input signals. A first switch branch in the first switch tree portion, which is constructed of a comparatively small number of MOSFETs, and a second switch branch in the second switch tree portion, which is constructed of a comparatively large number of MOSFETs, are controlled 'one' and 'off' by the same input signal, while a second switch branch in the first switch tree portion, which is constructed of a comparatively large number of MOSFETs, and a first switch branch in the second switch tree portion, which is constructed of a comparatively small number of MOSFETs, are controlled 'on' and 'off' by the same input signal. This construction is effective to lessen an increase in the number of MOSFETs which are to be coupled to the input lines of the address decoder.</description><edition>5</edition><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; PULSE TECHNIQUE ; STATIC STORES</subject><creationdate>1994</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940202&DB=EPODOC&CC=JP&NR=H069116B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940202&DB=EPODOC&CC=JP&NR=H069116B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OOKUBO CHIKAO</creatorcontrib><creatorcontrib>TACHIMORI HIROSHI</creatorcontrib><creatorcontrib>FUKUDA HIROSHI</creatorcontrib><creatorcontrib>FUKAZAWA TAKESHI</creatorcontrib><creatorcontrib>TAKAHASHI OSAMU</creatorcontrib><title>JPH069116B</title><description>A semiconductor integrated circuit device has an address decoder which is constructed of a plurality of MOSFETs implemented in a switch tree. The switch tree includes first and second switch tree portions which are controlled 'on' and 'off' by the same input signals. A first switch branch in the first switch tree portion, which is constructed of a comparatively small number of MOSFETs, and a second switch branch in the second switch tree portion, which is constructed of a comparatively large number of MOSFETs, are controlled 'one' and 'off' by the same input signal, while a second switch branch in the first switch tree portion, which is constructed of a comparatively large number of MOSFETs, and a first switch branch in the second switch tree portion, which is constructed of a comparatively small number of MOSFETs, are controlled 'on' and 'off' by the same input signal. This construction is effective to lessen an increase in the number of MOSFETs which are to be coupled to the input lines of the address decoder.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1994</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZODyCvAwMLM0NDRz4mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8QgNTkbGxKgBADGfG6Y</recordid><startdate>19940202</startdate><enddate>19940202</enddate><creator>OOKUBO CHIKAO</creator><creator>TACHIMORI HIROSHI</creator><creator>FUKUDA HIROSHI</creator><creator>FUKAZAWA TAKESHI</creator><creator>TAKAHASHI OSAMU</creator><scope>EVB</scope></search><sort><creationdate>19940202</creationdate><title>JPH069116B</title><author>OOKUBO CHIKAO ; TACHIMORI HIROSHI ; FUKUDA HIROSHI ; FUKAZAWA TAKESHI ; TAKAHASHI OSAMU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH069116BB23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1994</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>OOKUBO CHIKAO</creatorcontrib><creatorcontrib>TACHIMORI HIROSHI</creatorcontrib><creatorcontrib>FUKUDA HIROSHI</creatorcontrib><creatorcontrib>FUKAZAWA TAKESHI</creatorcontrib><creatorcontrib>TAKAHASHI OSAMU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>OOKUBO CHIKAO</au><au>TACHIMORI HIROSHI</au><au>FUKUDA HIROSHI</au><au>FUKAZAWA TAKESHI</au><au>TAKAHASHI OSAMU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>JPH069116B</title><date>1994-02-02</date><risdate>1994</risdate><abstract>A semiconductor integrated circuit device has an address decoder which is constructed of a plurality of MOSFETs implemented in a switch tree. The switch tree includes first and second switch tree portions which are controlled 'on' and 'off' by the same input signals. A first switch branch in the first switch tree portion, which is constructed of a comparatively small number of MOSFETs, and a second switch branch in the second switch tree portion, which is constructed of a comparatively large number of MOSFETs, are controlled 'one' and 'off' by the same input signal, while a second switch branch in the first switch tree portion, which is constructed of a comparatively large number of MOSFETs, and a first switch branch in the second switch tree portion, which is constructed of a comparatively small number of MOSFETs, are controlled 'on' and 'off' by the same input signal. This construction is effective to lessen an increase in the number of MOSFETs which are to be coupled to the input lines of the address decoder.</abstract><edition>5</edition><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng
recordid	cdi_epo_espacenet_JPH069116BB2
source	esp@cenet
subjects	BASIC ELECTRONIC CIRCUITRY ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE STATIC STORES
title	JPH069116B
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-26T22%3A27%3A49IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=OOKUBO%20CHIKAO&rft.date=1994-02-02&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPH069116BB2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true