JPH0685568B

PURPOSE:To attain high-speed decoding by sweeping out a line synchronizing code from a storage circuit in succession to a compression code after decoding at the detection of the line synchronizing code. CONSTITUTION:The compression code including a line synchronizing code is stored in a register 103 via a multiplexer 102 from a storage circuit 101. Then a code/decode logic 104 and a code table ROM105 apply a picture code and an EOL detection circuit 112 detects a line synchronizing code and at the decoding of the picture code, a multiplexer 102 is shifted by the code length of the decoded code to sweep out the compression code from the register 103. When an output of the EOL detection circuit is obtained in this case, the decoded code and the line synchronizing code are swept out. Thus, the time for decoding processing of the line synchronizing code is decreased and high-speed decoding is attained.