JPH0682689B

A process for formation of a GaAs MESFET for use in digital IC and MMIC is disclosed, the MESFET having a high operating speed and low noise characteristics. A multilayer resist comprising a nitride film, a photo resist, a titanium deposition layer, and a SiO layer made by SOG (spin-on-glass) is formed, and a gate which is formed in the length of 0.7-1 mu m by applying the photo transfer method is transcribed in the length of 0.3-0.5 mu m. The pattern of the gate is transcribed by etching it down to GaAs, and the place for the positioning of the T-shaped gate is defined by depositing tungsten silicide and by side-etching the photo resist. The T-shaped gate is manufactured by electroplating gold, and by lifting off the rest of the portions. The source and drain are then formed in a self-aligned manner by ion-implanting to a high concentration, and then a heat treatment is carried out to make active. A resistant contact is then formed by applying the photo transfer method and an etching, and is completed by depositing AuGe/Ni and by carrying out an alloy-treatment. A conventional metallization is then performed to complete the self-aligned gaAs MESFET having a T-shaped gate.