INTEGRATED CIRCUIT

PURPOSE:To contrive the basic operations of an SDRAM such as a serial accessing, and lap accessing at a synchronous DRAM. CONSTITUTION:The condition of a column select drive line/CDRV is decoded by one of plural column decoders 31 and 32 selected by partial decoders 41 and 42, plural column selecting signals CSL0 to CSL7 are generated and the column selection of a core part 5 is carried out. The data lines DQ0 to DQ3 of the core part 5 are selectively connected to read/write data lines RWD0 to RWD1 by a data buffer 2. The data of the read/write data lines RWD0 and RWD1 are selectively connected to the outside by a data register 1 in accordance with signals R1 and R2 based on a tap address. Thus, the core part 5 is switched by the tap address and the access is enabled.