COMPUTER-SYSTEM

PURPOSE: To incorporate parallel array processors on a single semiconductor silicon chip. CONSTITUTION: The parallel array processors for a large scale parallel application are formed by a low-output CMOS provided with a DRAM processing mechanism and processing elements are incorporated in single chip. The eight pieces of the processors in the single chip are provided with the processing elements, a large-scale memory and an input/output mechanism connected to themselves and connected with each other by corrected topology based on a hypercube. The nodes are then connected with each other by hypercube network topology, corrected hypercube network topology, ring network topology or intra-ring ring network topology. That is, they are connected with each other as an (n)-dimensional network cluster and produce a processing array and further, a cluster controller for a node array is provided.