COMPUTER-SYSTEM

PURPOSE: To incorporate parallel array processors on a single semiconductor silicon chip. CONSTITUTION: The parallel array processors for large scaled parallel application are formed by low output CMOS provided with a DRAM processing mechanism and processing elements are incorporated on a single chip. The eight processors on the single chip have the processing elements connected to themselves, large scaled memories and input/output mechanisms and they are connected by a corrected topology based on a hypercube. Nodes are connected by a hypercube network topology, a corrected hypercube network topology, a ring network topology or an intra-ring network topology. A programmable router for route-designating data and control information between memory processor memories and between computer system nodes is provided.