SEMICONDUCTOR MEMORY DEVICE

PURPOSE:To simultaneously achieve the low power consumption and the high- speed read/write operation of a RAM in a standby state. CONSTITUTION:In a diode load-type memory cell 10, an n type diffused layer 2 is formed at the lower side of a p-type diffused layer 5 constituting a high- resistance load...

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Bibliographische Detailangaben
Hauptverfasser: IWABUCHI MASATO, USAMI MASAMI
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To simultaneously achieve the low power consumption and the high- speed read/write operation of a RAM in a standby state. CONSTITUTION:In a diode load-type memory cell 10, an n type diffused layer 2 is formed at the lower side of a p-type diffused layer 5 constituting a high- resistance load R2, a power-supply voltage VCC is applied to the n type diffused layer 2, and a word-line potential VX is applied to one end part 5a in a p-type diffused layer 5. A depletion layer whose size corresponds to the difference between the word-line potential VX and the VCC is formed in a p-n junction face 5A between the p-type diffused layer 5 and an epitaxial layer 3, and the resistance value R2 of the p-type diffused layer 5 is changed. By using a change in a resistance value according to a change in two potential differences, the resistance value in a standby state is set to a comparatively large value (80kOMEGA), and that in a read/write state is set to a small value (40kOMEGA). Thereby, an inversion time constant in the read/write state becomes small, a high-speed operating property is enhanced, a holding current IST in the standby state can be reduced, and the power consumption of the title memory device can be lowered by its portion.