DATA PROCESSOR

PURPOSE:To match data stored in a cache memory with data stored in a corresponding address of a storage device at all times by providing a bus monitor device which compares the address latch of a write buffer with an address signal on a signal bus. CONSTITUTION:While another bus master attains write access to the storage device 9, a bus monitor device 73 compares the address held in the address latch 72 in the write buffer with the address signal on the signal line bus 8 and sends an interruption signal to a central processing unit 5 when they match each other. Further, when the address held in the address latch 72 matches the address signal on the signal line 8 while another bus master attains read access to the storage device 9, the bus monitor device 73 sends an output inhibition signal to a two-way buffer 10 and an R/W controller 11. At the same time, the data held in a data latch 71 are outputted to the signal line bus 8.