CLOCK ABNORMALITY DETECTING CIRCUIT

PURPOSE:To provide the clock abnormality detecting circuit which easily detects the frequency abnormality of an input clock. CONSTITUTION:This circuit consists of an input count part 20 which divides the frequency of the clock inputted to a PLO 10 by 1/N, an output count part 30 which divides the fr...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: KURABE MITSURU, NARAHIRA SADAO, SHINOMIYA TADANAO, OBA MASASHI, HIRATA TERUHIKO
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:PURPOSE:To provide the clock abnormality detecting circuit which easily detects the frequency abnormality of an input clock. CONSTITUTION:This circuit consists of an input count part 20 which divides the frequency of the clock inputted to a PLO 10 by 1/N, an output count part 30 which divides the frequency of the clock outputted from the PLO 10 by 1/N and slips the output pulse by a prescribed extent at the time of input of a slip pulse, a phase comparing part 40 which compares phases of output pulses of two count parts 20 and 30 with each other and outputs the slip pulse at the time of detecting prescribed phase deviation, and a slip counter part 50 which counts the slip pulse outputted from the phase comparing part 40 and discriminates the clock abnormality to output a clock abnormality signal at the time of counting a prescribed number of pulses within a certain time.