FLIP FLOP CIRCUIT

PURPOSE:To increase the operation speed by shortening the transmission delay time and, the setup time of an edge trigger type flip flop circuit. CONSTITUTION:This circuit consists of a data transmission part DT1 which includes a pair of tristate gates TG1 and TG2 and selectively transmits non- inver...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: KAWADA ATSUMI, YOSHIHARA KAZUHIRO, TANAKA HIRONORI, YAMASHITA HIROKI, NAGAI KENJI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To increase the operation speed by shortening the transmission delay time and, the setup time of an edge trigger type flip flop circuit. CONSTITUTION:This circuit consists of a data transmission part DT1 which includes a pair of tristate gates TG1 and TG2 and selectively transmits non- inverting input data DT and inverting input data DB in accordance with a non-inverting clock signal CK, a data holding part DB1 which includes a pair of cross-connected inverters N1 and N2 having a driving capability lower than that of tristate gates TG1 and TG2 and holds an inverting output signal MB and a non-inverting output signal MT of the data transmission part DT1, a data transmission part DT2 having the same constitution as the part DT1, and a data holding part DB2 having the same constitution as the part DB1, and the transmission delay time and the setup time are shortened to the delay time of one stage of tristate gates.