JPH0628302B

PURPOSE:To prevent short circuits among signal lines and power supply lines by pulling up the potential of bit lines to potential higher than that of the power supply lines and arranging the bit lines and the power supply lines so that spaces among the bit lines to each bit line pair and the power s...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: YAMAUCHI TAKAHIKO, AOYAMA KEIZO
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To prevent short circuits among signal lines and power supply lines by pulling up the potential of bit lines to potential higher than that of the power supply lines and arranging the bit lines and the power supply lines so that spaces among the bit lines to each bit line pair and the power supply lines are made wider than spaces among adjacent bit line pairs. CONSTITUTION:The potential of bit lines is pulled up to potential higher than that of power supply lines, and spaces among the bit lines in each bit line pair and the power supply lines are made wider than spaces among adjacent bit line pairs. The bit line such as a bit line -BL0 is separated from the power supply line Vss, and brought close to another bit line BL1 by a section corresponding to the separating section. Consequently, a defective short circuit between the bit line -BL0 and the bit line BL1 is easy to be generated, but a critical short circuit between the bit line -BL0 and the power supply line Vss can be prevented. As a result, the bit lines and the power supply lines are separated by asymmetrically arranging the bit lines to contact regions CONTs, and critical short circuits can be obviated. Accordingly, the relief probability of defects by a redundancy circuit can be enhanced.