INSULATED GATE BIPOLAR TRANSISTOR

PURPOSE:To provide an insulated gate bipolar transistor wherein a parasitic thyristor is protected against latch-up and lessened in turn-OFF time. CONSTITUTION:In an insulated gate bipolar transistor, a potential barrier to majority carriers in a collector layer is provided in a base layer adjacent...

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Bibliographische Detailangaben
Hauptverfasser: MARUYAMA KISHIKO, KANBARA SHIRO, TAKAHASHI MAKOTO, MATSUO HITOSHI, TOYABE TATSU, ITO SATOSHI, TANAKA JUNKO, OKURA YASUYUKI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To provide an insulated gate bipolar transistor wherein a parasitic thyristor is protected against latch-up and lessened in turn-OFF time. CONSTITUTION:In an insulated gate bipolar transistor, a potential barrier to majority carriers in a collector layer is provided in a base layer adjacent to the collector layer, whereby majority carriers in the collector layer are stopped from being injected into a region which extends from a part under a gate electrode 16 of the base layer adjacent to the collector layer to a region except under an emitter electrode 15. Majority carriers in the collector layer are prevented from flowing towards the emitter electrode 15 via the base layer adjacent to the emitter layer 4 from a region under the gate electrode 16 of the base layer adjacent to the collector layer or a region except under the emitter electrode 15. By this setup, a parasitic thyristor can be protected against latch-up and/or lessened in turn-OFF time without deteriorating other characteristics.