MEMORY CONTROLLER AND DATA PROCESSOR

MEMORY CONTROLLER AND DATA PROCESSOR

PURPOSE:To simplify hardware constitution when plural memories different in cycle time can be used in a common system. CONSTITUTION:A memory controller 44 is formed by including an address register 3 holding wait information of cycle time for the respective memories different in cycle time and an RD...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: ETO YOICHIRO, SAIE YASUHIKO, EGAWA HIDEKAZU, OOKUBO CHIKAO, NISHIMOTO KENJI, KIKUCHI TAKASHI, WATANABE AKIO, KUMAGAI TATSUHIKO
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:PURPOSE:To simplify hardware constitution when plural memories different in cycle time can be used in a common system. CONSTITUTION:A memory controller 44 is formed by including an address register 3 holding wait information of cycle time for the respective memories different in cycle time and an RDY* signal generation circuit 1 generating RDY 3 for deciding a bus cycle in memory access based on holding information of the address register 3 at the time of memory access. Hardware constitution is simplified by using the memory controller compared to a case when a circuit having the similar signal generation function is formed by TTL and the like.