HIGH ELECTRON NOBILITY TRANSISTOR AND MANUFACTURE THEREOF
PURPOSE:To decrease both the stray capacitance between a gate electrode and a source and drain electrode and the parasitic resistance between the source and drain and a channel part. CONSTITUTION:At least a channel layer 4, an electron feeding layer 5, source and drain electrodes 6s and 6d, and a ga...
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creator | KAMATA MIKIO |
description | PURPOSE:To decrease both the stray capacitance between a gate electrode and a source and drain electrode and the parasitic resistance between the source and drain and a channel part. CONSTITUTION:At least a channel layer 4, an electron feeding layer 5, source and drain electrodes 6s and 6d, and a gate electrode 7 are provided on a semiconductor substrate 3, the source and drain electrodes 6s and 6d are brought into contact with the side face of the channel layer 4, and the upper surfaces 6ss and 6ds of the source and the drain electrodes 6s and 6d are positioned almost on the same place surface of the bottom face 7b of the gate electrode 7 or lower than that. |
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CONSTITUTION:At least a channel layer 4, an electron feeding layer 5, source and drain electrodes 6s and 6d, and a gate electrode 7 are provided on a semiconductor substrate 3, the source and drain electrodes 6s and 6d are brought into contact with the side face of the channel layer 4, and the upper surfaces 6ss and 6ds of the source and the drain electrodes 6s and 6d are positioned almost on the same place surface of the bottom face 7b of the gate electrode 7 or lower than that.</description><edition>5</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1994</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940902&DB=EPODOC&CC=JP&NR=H06244219A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940902&DB=EPODOC&CC=JP&NR=H06244219A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KAMATA MIKIO</creatorcontrib><title>HIGH ELECTRON NOBILITY TRANSISTOR AND MANUFACTURE THEREOF</title><description>PURPOSE:To decrease both the stray capacitance between a gate electrode and a source and drain electrode and the parasitic resistance between the source and drain and a channel part. CONSTITUTION:At least a channel layer 4, an electron feeding layer 5, source and drain electrodes 6s and 6d, and a gate electrode 7 are provided on a semiconductor substrate 3, the source and drain electrodes 6s and 6d are brought into contact with the side face of the channel layer 4, and the upper surfaces 6ss and 6ds of the source and the drain electrodes 6s and 6d are positioned almost on the same place surface of the bottom face 7b of the gate electrode 7 or lower than that.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1994</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLD08HT3UHD1cXUOCfL3U_Dzd_L08QyJVAgJcvQL9gwO8Q9ScPRzUfB19At1c3QOCQ1yVQjxcA1y9XfjYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxXgEeBmZGJiZGhpaOxsSoAQCs3Sk0</recordid><startdate>19940902</startdate><enddate>19940902</enddate><creator>KAMATA MIKIO</creator><scope>EVB</scope></search><sort><creationdate>19940902</creationdate><title>HIGH ELECTRON NOBILITY TRANSISTOR AND MANUFACTURE THEREOF</title><author>KAMATA MIKIO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH06244219A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1994</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KAMATA MIKIO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KAMATA MIKIO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>HIGH ELECTRON NOBILITY TRANSISTOR AND MANUFACTURE THEREOF</title><date>1994-09-02</date><risdate>1994</risdate><abstract>PURPOSE:To decrease both the stray capacitance between a gate electrode and a source and drain electrode and the parasitic resistance between the source and drain and a channel part. CONSTITUTION:At least a channel layer 4, an electron feeding layer 5, source and drain electrodes 6s and 6d, and a gate electrode 7 are provided on a semiconductor substrate 3, the source and drain electrodes 6s and 6d are brought into contact with the side face of the channel layer 4, and the upper surfaces 6ss and 6ds of the source and the drain electrodes 6s and 6d are positioned almost on the same place surface of the bottom face 7b of the gate electrode 7 or lower than that.</abstract><edition>5</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | HIGH ELECTRON NOBILITY TRANSISTOR AND MANUFACTURE THEREOF |
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