DYNAMIC RAM AND DATA PROCESSING SYSTEM THEREOF

PURPOSE:To compensate the dispersion of the threshold voltage of a MOS transistor and to apply to the main storage memory of a low cost and large capacity data processing system by improving coupling capacity in the differential amplifier of a DRAM. CONSTITUTION:In the intersection between a bit line BL and a word line WL, plural memory cells as shown in the memory cells 1 and 2 connected with word lines WL1 and WL2 are constituted. These memory cells are DRAM. As a sense amplifier, P type sense amplifiers PSA 1 and PSA 2 are constituted or an N type sense amplifier NSA is constituted, and a precharge circuit PC is constituted between the amplifier PSA 1 and the NSA. A normal operation is guranteed by imparting the voltage corresponding to the threshold voltage difference of NMOSTr Q6 and Q5 to the source side of the NMOS transistor (Tr) Q5 by these sense amplifiers and by performing the preamplifying due to the coupling for which capacitors C1 and C2 are used.