COMPUTER SYSTEM

PURPOSE: To provide a new large-scaled parallel processor and computer system. CONSTITUTION: A parallel array processor for a large-scaled parallel application is formed of a low output CMOS equipped with a DRAM processing mechanism, and processing elements are integrated on a single chip. Eight pro...

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Hauptverfasser: MAIKERU CHIYAARUZU DATSUPU, DONARUDO MAIKERU RESUMAISUTAA, BUINSENTO JIYON SUMOORARU, TOMASU NOOMAN BAAKAA, BIRII JIYATSUKU NOURUZU, DONARUDO JIYOOJI GURAISU, JIEEMUZU ROBAATO SUTATSUPU, DEEBUITSUDO BURUUSU RORUFU, RICHIYAADO AANESUTO MAIRUZU, ERITSUKU YUUJIN RETAA, DEEBUITSUDO KURISUTOFUAA KUCHINSUKI, JIEEMUZU UOREN DEIIFUENDERUFUAA, POORU ANBA UIRUKINSON, ROBAATO RAISUTO RICHIYAADOSON, KURAIBU ARAN KORINZU, RICHIYAADO EDOWAADO NAIYAA, PIITAA MAIKERU KOTSUHE, NIKORASU JIEROOMU SHIYOONOBUAA
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE: To provide a new large-scaled parallel processor and computer system. CONSTITUTION: A parallel array processor for a large-scaled parallel application is formed of a low output CMOS equipped with a DRAM processing mechanism, and processing elements are integrated on a single chip. Eight processors on the signal chip are provided with the processing elements, large-scaled memory, and input and output mechanism connected with themselves, and they are interconnected by a corrected topology, based on a hyper cube. Those nodes are interconnected by a hyper cube network topology, corrected hyper cube network topology, ring network topology, or in-ring ring network topology.