METHOD FOR VERIFYING LOGIC DEVICE
PURPOSE:To speed up logic verification by eliminating the need to input an invariant conditional expression for the logic verification by a user, to decreas ing a calculation quantity by the use of a mathematical inductive method, and handling a logic circuit for a multi-phase clock. CONSTITUTION:Re...
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| creator | SHONAI TORU SHIMIZU TSUGUO |
| description | PURPOSE:To speed up logic verification by eliminating the need to input an invariant conditional expression for the logic verification by a user, to decreas ing a calculation quantity by the use of a mathematical inductive method, and handling a logic circuit for a multi-phase clock. CONSTITUTION:Realized specifications 100 of the logic device which is controlled with the multi-phase clock are converted into realized specifications 104 in register transfer description in recurrent function format which are controlled with a single clock (stages 1101 and 1102). The realized specifications 104 are converted into realized specifications 108 in operation description in recurrent function format (state 1301). The realized specifications 108 are converted into realized specifications in operation description in 2nd recurrent function format and it is proved that the realized specifications in operation description in 2nd recurrent function format are equal to external specifications 110 in recurrent function format. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH06215063A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH06215063A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH06215063A3</originalsourceid><addsrcrecordid>eNrjZFD0dQ3x8HdRcPMPUghzDfJ0i_T0c1fw8Xf3dFZwcQ3zdHblYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxXgEeBmZGhqYGZsaOxsSoAQANISIx</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD FOR VERIFYING LOGIC DEVICE</title><source>esp@cenet</source><creator>SHONAI TORU ; SHIMIZU TSUGUO</creator><creatorcontrib>SHONAI TORU ; SHIMIZU TSUGUO</creatorcontrib><description>PURPOSE:To speed up logic verification by eliminating the need to input an invariant conditional expression for the logic verification by a user, to decreas ing a calculation quantity by the use of a mathematical inductive method, and handling a logic circuit for a multi-phase clock. CONSTITUTION:Realized specifications 100 of the logic device which is controlled with the multi-phase clock are converted into realized specifications 104 in register transfer description in recurrent function format which are controlled with a single clock (stages 1101 and 1102). The realized specifications 104 are converted into realized specifications 108 in operation description in recurrent function format (state 1301). The realized specifications 108 are converted into realized specifications in operation description in 2nd recurrent function format and it is proved that the realized specifications in operation description in 2nd recurrent function format are equal to external specifications 110 in recurrent function format.</description><edition>5</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1994</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940805&DB=EPODOC&CC=JP&NR=H06215063A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940805&DB=EPODOC&CC=JP&NR=H06215063A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SHONAI TORU</creatorcontrib><creatorcontrib>SHIMIZU TSUGUO</creatorcontrib><title>METHOD FOR VERIFYING LOGIC DEVICE</title><description>PURPOSE:To speed up logic verification by eliminating the need to input an invariant conditional expression for the logic verification by a user, to decreas ing a calculation quantity by the use of a mathematical inductive method, and handling a logic circuit for a multi-phase clock. CONSTITUTION:Realized specifications 100 of the logic device which is controlled with the multi-phase clock are converted into realized specifications 104 in register transfer description in recurrent function format which are controlled with a single clock (stages 1101 and 1102). The realized specifications 104 are converted into realized specifications 108 in operation description in recurrent function format (state 1301). The realized specifications 108 are converted into realized specifications in operation description in 2nd recurrent function format and it is proved that the realized specifications in operation description in 2nd recurrent function format are equal to external specifications 110 in recurrent function format.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1994</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFD0dQ3x8HdRcPMPUghzDfJ0i_T0c1fw8Xf3dFZwcQ3zdHblYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxXgEeBmZGhqYGZsaOxsSoAQANISIx</recordid><startdate>19940805</startdate><enddate>19940805</enddate><creator>SHONAI TORU</creator><creator>SHIMIZU TSUGUO</creator><scope>EVB</scope></search><sort><creationdate>19940805</creationdate><title>METHOD FOR VERIFYING LOGIC DEVICE</title><author>SHONAI TORU ; SHIMIZU TSUGUO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH06215063A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1994</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>SHONAI TORU</creatorcontrib><creatorcontrib>SHIMIZU TSUGUO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SHONAI TORU</au><au>SHIMIZU TSUGUO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD FOR VERIFYING LOGIC DEVICE</title><date>1994-08-05</date><risdate>1994</risdate><abstract>PURPOSE:To speed up logic verification by eliminating the need to input an invariant conditional expression for the logic verification by a user, to decreas ing a calculation quantity by the use of a mathematical inductive method, and handling a logic circuit for a multi-phase clock. CONSTITUTION:Realized specifications 100 of the logic device which is controlled with the multi-phase clock are converted into realized specifications 104 in register transfer description in recurrent function format which are controlled with a single clock (stages 1101 and 1102). The realized specifications 104 are converted into realized specifications 108 in operation description in recurrent function format (state 1301). The realized specifications 108 are converted into realized specifications in operation description in 2nd recurrent function format and it is proved that the realized specifications in operation description in 2nd recurrent function format are equal to external specifications 110 in recurrent function format.</abstract><edition>5</edition><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | METHOD FOR VERIFYING LOGIC DEVICE |
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