SEMICONDUCTOR MEMORY
PURPOSE:To equalize the varied quantity of the write pulse width and the cell inversion time regardless of the change of element characteristics by writing and reading information in and from a dual port dummy memory cell responding in the same manner as a memory cell and detecting information inver...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | PURPOSE:To equalize the varied quantity of the write pulse width and the cell inversion time regardless of the change of element characteristics by writing and reading information in and from a dual port dummy memory cell responding in the same manner as a memory cell and detecting information inversion to determine the write pulse width. CONSTITUTION:A dual port write circuit DW of a write pulse generating circuit WPG writes information in a dual port dummy memory cell DPC which is provided with write and read ports WP and RP and responds in the same manner as a memory cell RAM. This information is read out, and a pulse generating circuit PG detects inversion of information of the memory cell to determine the pulse width and outputs a write pulse WE. By this constitution, varied quantity of the write pulse width and the inversion time of the cell become same regardless of the change of element characteristics, and the timing margin is reduced, and this semiconductor memory becomes a high-speed operation cycle. |
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