MASTER SLICE TYPE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PURPOSE:To realize the change of writing data at a low cost in a short period of time by a method wherein the writing and reading of data in a read-only memory circuit are effected by the connection of wirings while the change of writing data is realized by the change of only a second via. CONSTITUT...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: OGUCHI YASUHIRO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator OGUCHI YASUHIRO
description PURPOSE:To realize the change of writing data at a low cost in a short period of time by a method wherein the writing and reading of data in a read-only memory circuit are effected by the connection of wirings while the change of writing data is realized by the change of only a second via. CONSTITUTION:A plurality of N-channel transistors 501, 502 are put on/off by a word line 506 to read out data to the same branch bit line 511. The number of transistors is determined by the charging and/or discharging time of a potential in a transistor with respect to the branch bit line of the transistor, which is determined by the relative positional relation of transistors, connected to a logical forward turning circuit 509 or connected to a logical inverting circuit 510 and the branch bit line 511, whereby the reading time of data is changed. By this method, high-speed read out can be realized when a P-channel transistor only is connected to the branch bit line or only a n-channel transistor is connected to the branch bit line.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH0613586A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH0613586A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH0613586A3</originalsourceid><addsrcrecordid>eNrjZLD0dQwOcQ1SCPbxdHZVCIkMcFUIdvX1dPb3cwl1DvEPUvD0C3F1D3IMcXVRcPYMcg71DFFwcQ0DKuZhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfFeAR4GZobGphZmjsZEKAEAWboowQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MASTER SLICE TYPE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE</title><source>esp@cenet</source><creator>OGUCHI YASUHIRO</creator><creatorcontrib>OGUCHI YASUHIRO</creatorcontrib><description>PURPOSE:To realize the change of writing data at a low cost in a short period of time by a method wherein the writing and reading of data in a read-only memory circuit are effected by the connection of wirings while the change of writing data is realized by the change of only a second via. CONSTITUTION:A plurality of N-channel transistors 501, 502 are put on/off by a word line 506 to read out data to the same branch bit line 511. The number of transistors is determined by the charging and/or discharging time of a potential in a transistor with respect to the branch bit line of the transistor, which is determined by the relative positional relation of transistors, connected to a logical forward turning circuit 509 or connected to a logical inverting circuit 510 and the branch bit line 511, whereby the reading time of data is changed. By this method, high-speed read out can be realized when a P-channel transistor only is connected to the branch bit line or only a n-channel transistor is connected to the branch bit line.</description><edition>5</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>1994</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19940121&amp;DB=EPODOC&amp;CC=JP&amp;NR=H0613586A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19940121&amp;DB=EPODOC&amp;CC=JP&amp;NR=H0613586A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OGUCHI YASUHIRO</creatorcontrib><title>MASTER SLICE TYPE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE</title><description>PURPOSE:To realize the change of writing data at a low cost in a short period of time by a method wherein the writing and reading of data in a read-only memory circuit are effected by the connection of wirings while the change of writing data is realized by the change of only a second via. CONSTITUTION:A plurality of N-channel transistors 501, 502 are put on/off by a word line 506 to read out data to the same branch bit line 511. The number of transistors is determined by the charging and/or discharging time of a potential in a transistor with respect to the branch bit line of the transistor, which is determined by the relative positional relation of transistors, connected to a logical forward turning circuit 509 or connected to a logical inverting circuit 510 and the branch bit line 511, whereby the reading time of data is changed. By this method, high-speed read out can be realized when a P-channel transistor only is connected to the branch bit line or only a n-channel transistor is connected to the branch bit line.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1994</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLD0dQwOcQ1SCPbxdHZVCIkMcFUIdvX1dPb3cwl1DvEPUvD0C3F1D3IMcXVRcPYMcg71DFFwcQ0DKuZhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfFeAR4GZobGphZmjsZEKAEAWboowQ</recordid><startdate>19940121</startdate><enddate>19940121</enddate><creator>OGUCHI YASUHIRO</creator><scope>EVB</scope></search><sort><creationdate>19940121</creationdate><title>MASTER SLICE TYPE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE</title><author>OGUCHI YASUHIRO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH0613586A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1994</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>OGUCHI YASUHIRO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>OGUCHI YASUHIRO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MASTER SLICE TYPE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE</title><date>1994-01-21</date><risdate>1994</risdate><abstract>PURPOSE:To realize the change of writing data at a low cost in a short period of time by a method wherein the writing and reading of data in a read-only memory circuit are effected by the connection of wirings while the change of writing data is realized by the change of only a second via. CONSTITUTION:A plurality of N-channel transistors 501, 502 are put on/off by a word line 506 to read out data to the same branch bit line 511. The number of transistors is determined by the charging and/or discharging time of a potential in a transistor with respect to the branch bit line of the transistor, which is determined by the relative positional relation of transistors, connected to a logical forward turning circuit 509 or connected to a logical inverting circuit 510 and the branch bit line 511, whereby the reading time of data is changed. By this method, high-speed read out can be realized when a P-channel transistor only is connected to the branch bit line or only a n-channel transistor is connected to the branch bit line.</abstract><edition>5</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JPH0613586A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
title MASTER SLICE TYPE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-10T20%3A00%3A58IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=OGUCHI%20YASUHIRO&rft.date=1994-01-21&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPH0613586A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true