MASTER SLICE TYPE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PURPOSE:To realize the change of writing data at a low cost in a short period of time by a method wherein the writing and reading of data in a read-only memory circuit are effected by the connection of wirings while the change of writing data is realized by the change of only a second via. CONSTITUT...

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1. Verfasser: OGUCHI YASUHIRO
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To realize the change of writing data at a low cost in a short period of time by a method wherein the writing and reading of data in a read-only memory circuit are effected by the connection of wirings while the change of writing data is realized by the change of only a second via. CONSTITUTION:A plurality of N-channel transistors 501, 502 are put on/off by a word line 506 to read out data to the same branch bit line 511. The number of transistors is determined by the charging and/or discharging time of a potential in a transistor with respect to the branch bit line of the transistor, which is determined by the relative positional relation of transistors, connected to a logical forward turning circuit 509 or connected to a logical inverting circuit 510 and the branch bit line 511, whereby the reading time of data is changed. By this method, high-speed read out can be realized when a P-channel transistor only is connected to the branch bit line or only a n-channel transistor is connected to the branch bit line.