ESTIMATING METHOD FOR WIRING LENGTH OF SEMICONDUCTOR INTEGRATED CIRCUIT

PURPOSE:To accurately estimate the wiring length of a semiconductor integrated circuit even in such a case that a large error is included in the estimated wiring length due to large-sized undesigned macros when the estimated wiring length is found at the time of performing the floor planning of an LSI. CONSTITUTION:In processes 2 and 3, already designed macros are arranged on a chip by estimated the size of the chip and, in process 5, undesigned macros are arranged and their sizes are estimated. Whether or not the estimated sizes of the macros meet the condition of allowable error limit for wiring length of the chip is discriminated and when the sizes of the macros are within the error limit, a wiring length estimating section calculates the wiring length from the inter-macro Manhattan distance in process 9. In process 9, the wiring length is estimated from the Manhattan distances between groups among the undesigned macros and macros. When some groups exceed the limit, the groups are divided and arranged and the size of each group is estimated at a low-rank hierarchy. By repeating the above-mentioned operations, the wiring estimation is performed after all wiring lengths fall within the allowable limit and delay simulation 10 is performed by using the estimated wiring length.